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TRIPLE INDEPENDENT LOGIC INTERFACED HALF BRIDGES
EBO2
MICROTECHNOLOGY
HTTP://WWW.APEXMICROTECH.COM
(800) 546-APEX
(800) 546-2739
FEATURES
* * * * * COMPATIBLE WITH PWM FREQUENCIES UP TO 50KHZ 10V TO 100 V MOTOR SUPPLY 10A CONTINUOUS OUTPUT CURRENT HCMOS COMPATIBLE SCHMITT TRIGGER LOGIC INPUTS SEPARATE SOURCE OUTPUTS FOR NEGATIVE RAIL CURRENT SENSE * SLEEP MODE * WIDE RANGE FOR GATE DRIVE AND LOGIC SUPPLIES
APPLICATIONS
HIGH POWER CIRCUITS FOR DIGITAL CONTROL OF: * THREE AXIS MOTION USING BRUSH TYPE MOTORS * THREE PHASE BRUSHLESS DC MOTOR DRIVE * THREE PHASE AC MOTOR DRIVE * THREE PHASE STEP MOTOR DRIVE
Hin 1 12 SD 11 Half Bridge Driver FET Half Bridge Output 13 14 HV1
OUT1
Lin 1 10 Vcc1 9
15
S1 HVRTN1
DESCRIPTION
The EB02 consists of three independent FET half bridges with drivers. The drivers may be interfaced with CMOS or HCMOS level logic.
16
Hin 2 Vss,Logic Ground
8
17 Half Bridge Driver FET Half Bridge Output
HV2
7
18
OUT2
Lin2 6
19 20
S2 HVRTN2
Vcc 2
5
Vdd,Logic Supply 4 Hin3 3 Half Bridge Driver Lin 3 2 FET Half Bridge Output 21 HV3
22
OUT3
23 24
S3 HVRTN3
Vcc 3 1
FIGURE 1. BLOCK DIAGRAM
APEX MICROTECHNOLOGY CORPORATION * TELEPHONE (520) 690-8600 * FAX (520) 888-3329 * ORDERS (520) 690-8601 * EMAIL prodlit@apexmicrotech.com 1
EB02
ABSOLUTE MAXIMUM RATINGS
MOTOR VOLTAGE SUPPLY, HV OUTPUT CURRENT, peak OUTPUT CURRENT, continuous1 GATE SUPPLY VOLTAGE, Vcc LOGIC SUPPLY VOLTAGE, Vdd POWER DISSIPATION, internal1 LOGIC INPUT VOLTAGE THERMAL RESISTANCE TO CASE3 TEMPERATURE, pin solder, 10s TEMPERATURE, junction2 TEMPERATURE RANGE, storage OPERATING TEMPERATURE, case TEST CONDITIONS IOUT=10A; Vcc=10.8V, Vdd=5V; HV=100V, Fpwm=50kHz, L=100 H " " " " " Set by external circuitry Set by internal resistors MIN 99.2 -1.5 TYP
ABSOLUTE MAXIMUM RATINGS SPECIFICATIONS
SPECIFICATIONS
PARAMETER POSITIVE OUTPUT VOLTAGE NEGATIVE OUTPUT VOLTAGE POSITIVE EDGE DELAY RISETIME NEGATIVE EDGE DELAY FALLTIME PWM FREQUENCY INPUT IMPEDANCE
100V 20A 10A 20V 20V 51 Watts -0.3V to Vdd + 0.3V 2.1C/Watt 300C 150C -55 to +150C -25 to +85C MAX 101.5 .8 260 50 310 50 50 50 UNITS Volts Volts n-second n-second n-second n-second kHz k-ohm
INPUT AND OUTPUT SIGNALS
PIN 1 2 3 4 5 6 7 8 9 10 11 12 NOTES: 1. 2. 3. SYMBOL Vcc3 Lin3 Hin3 Vdd Vcc2 Lin2 Vss Hin2 Vcc1 Lin1 SD Hin1 FUNCTION Gate supply 3 Low drive logic in 3 High drive logic in 3 Logic supply Gate supply 2 Low drive logic in 2 Signal ground High drive logic in 2 Gate supply 1 Low drive logic in 1 Shut down logic in High drive logic in 1 PIN 13 14 15 16 17 18 19 20 21 22 23 24 SYMBOL HV1 OUT1 S1 HVRTN1 HV2 OUT 2 S2 HVRTN2 HV3 OUT 3 S3 HVRTN 3 FUNCTION High Voltage supply 1 Section 1 output Section 1 source Section 1 return High voltage supply 2 Section 2 output Section 2 source Section 2 return High voltage supply 3 Section 3 output Section 3 source Section 3 return
Over full operating temperature range. Long term operation at the maximum junction temperature will result in reduced product life. Lower internal temperature by reducing internal dissipation or using better heatsinking to achieve high MTTF. Each FET.
INPUT
A logic level input independently controls each FET in the half bridge. A logic level high turns on the FET and low turns it off. A common shut down input turns off all FETs when high. All inputs are Schmitt triggers with the upper threshold at 2/3 Vdd and the lower threshold at 1/3 Vdd. This comfortably interfaces with CMOS or HCMOS provided that the Vdd for the logic family and the EB02 are the same. TTL families may be used if a pull-up to Vcc is added to the TTL gates driving the EB02, and Vdd for the EB02 is the same supply as Vcc for the TTL family. An open signal connector pulls the shut down input high and all other inputs low, insuring that all outputs are off.
However, input impedance is 50k on all inputs; therefore, if one input is open circuited a high radiated noise level could spuriously turn on a FET.
OUTPUT
Each output section consists of a switching mode FET half bridge. Separate HV supply, emitter, and HV return lines are provided for each section. The FETs are conservatively rated to carry 10A. At 10A the saturation voltage is 1.5 V maximum, over the full environmental range. Each FET has an intrinsic diode connected in anti-parallel. When switching an inductive load this diode will conduct, and the drop at 10A will be 1.5V maximum, over the full environmental range.
APEX MICROTECHNOLOGY CORPORATION * 5980 NORTH SHANNON ROAD * TUCSON, ARIZONA 85741 * USA * APPLICATIONS HOTLINE: 1 (800) 546-2739 2
PACKAGE SPECIFICATIONS
EB02
PACKAGE SPECIFICATIONS DIP9 PACKAGE
WEIGHT: 69 g or 2.4 oz DIMENSIONS ARE IN INCHES ALTERNATE UNITS ARE [MM]
APEX MICROTECHNOLOGY CORPORATION * TELEPHONE (520) 690-8600 * FAX (520) 888-3329 * ORDERS (520) 690-8601 * EMAIL prodlit@apexmicrotech.com 3
OPERATING CONSIDERATIONS
EB02
current. (The size of the antenna.) Therefore, the 1F ceramic capacitors should bypass each HV to its return at the pins of the EB02.
POWER SUPPLY REQUIREMENTS
SUPPLY HV1 HV2 HV3 Vcc1 Vcc2 Vcc3 Vdd VOLTAGE 10V to 100V 10V to 100V 10V to 100V 10V to 20V 10V to 20V 10V to 20V 4.5 to 20V MAX CURRENT 10A, continuous, 20A peak 10A, continuous, 20A peak 10A, continuous, 20A peak 10mA 10mA 10mA 10mA
SHOOT THROUGH PROTECTION
Power FETs have a relatively short turn on delay, and a long turn off delay. Therefore, if the turn on input to an FET in a half bridge circuit is applied simultaneously with the turn off input to the other FET in that half bridge, there will be a time when both FETs are simultaneously on. This "shoot through condition" will short the power rails through the FETs, causing excessive power dissipation and very high EMI. To avoid the shoot through condition the turn on of one FET must be delayed long enough for the other FET in the same half bridge to have completely turned off. A delay of at least 0.5 -seconds is required for the EB02. This delay is required for both the Hin and Lin inputs.
HV1, HV2, and HV3 may be used independently, or may be one supply. Also Vcc1, Vcc2, and Vcc3 may be used independently or tied together. The Vdd supply must be compatible with the input logic. If a high voltage logic such as CMOS is used it may be tied with the Vcc supplies. HCMOS requires a 5V10% supply
SPECIAL CONSIDERATIONS GENERAL
The EB02 is designed to give the user maximum flexibility in a digital or DSP based motion control system. Thermal, overvoltage, overcurrent, and crossfire protection circuits are part of the user's design. Users should read Application Note 1, "General Operating Considerations;" and Application Note 30, "PWM Basics" for much useful information in applying this part. These Application Notes are in the "Power Integrated Circuits Data Book" and on line at www.apexmicrotech.com.
PROTECTION CIRCUITS
The EB02 does not include protection circuits. However, there is a shut down input which will turn off all FETs when at logic "1". This input may be used with user designed temperature sensing and current sensing circuits to shut down the FETs in the event of a detected unsafe condition. This is recommended since the FETs may be turned off this way even if the normal input logic or DSP programming is faulty.
START UP CONSIDERATIONS
The lower rail FET in the half bridge must be turned on for at least 2 -seconds to charge the bootstrap capacitor before the top rail FET can be turned on. This must be done no more than 330 -seconds prior to turning on the top rail FET. However, a grounded load will give the same purpose as turning on the lower rail FET. However a grounded load will give the same purpose as turning on the lower rail FET. Therefore a grounded load may be operated without this consideration. An internal floating supply is used to enhance the operation of the bootstrap bias circuit. This allows the top rail FETs to be held on indefinitely once turned on.
GROUNDING AND BYPASSING
As in any high power PWM system, grounding and bypassing are some of the keys to success. The EB02 is capable of generating 2 kW pulses with 40 n-second rise and fall times. If improperly grounded or bypassed this can cause horrible conducted and radiated EMI. In order to reduce conducted EMI, the EB02 provides a separate power ground, named HVRTN, for each high voltage supply. These grounds are electrically isolated from the logic ground and each other. This isolation eliminates high current ground loops. However, more than 5V offset between the grounds will destroy the EB02. Apex recommends back to back high current diodes between logic and power grounds; this will maintain isolation but keep offset at a safe level. All grounds should tie together at one common point in the system. In order to reduce radiated EMI, Apex recommends a 100 F or larger capacitor between HV and HVRTN. This capacitor should be a switching power grade capacitor with ESR rated at 20kHz. This capacitor should be placed physically as close to the EB02 as possible. However, such a capacitor will typically have a few hundred milli-ohms or so ESR. Therefore, each section must also be bypassed with a low ESR 1F or larger ceramic capacitor. In order to minimize radiated noise, it is necessary to minimize the area of the loop containing high frequency
HEATSINK
The EB02 should be provided with sufficient heatsink to dissipate 51 watts when operating at 100V, 10A, 50kHz and 3 sections simultaneously providing maximum current. The dissipation is composed of conduction losses (I out xV sat ) up to 16 watt per half bridge and switching losses of about 1 watt per half bridge. The conduction losses are proportional to Iout; switching losses are proportional to HV supply voltage, load capacitance, and switching frequency.
This data sheet has been carefully checked and is believed to be reliable, however, no responsibility is assumed for possible inaccuracies or omissions. All specificiations are subject to change without notice. APEX MICROTECHNOLOGY CORPORATION * 5980 NORTH SHANNON ROAD * TUCSON, ARIZONA 85741 * USA * APPLICATIONS HOTLINE: 1 (800) 546-2739 EBO2U REV. B JANUARY 2001 (c) 2001 Apex Microtechnology Corporation
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